1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC), and more particularly, to a pumping voltage generating circuit.
2. Related Art
In general, a dynamic random access memory (DRAM) device is capable of reading or writing data to a memory cell composed of a transistor and a capacitor. Since a DRAM device uses NMOS transistors comprising the memory cell, it includes a voltage pumping circuit for driving a word line to generate a potential at a level higher than the combined voltages of an external power supply voltage VDD and a threshold voltage Vt due to voltage losses due to the threshold voltage Vt.
For example, in order to drive an NMOS transistor in a DRAM memory cell, a voltage, which is higher than a source voltage by an amount equal to the threshold voltage Vt, should be applied to a gate of the NMOS transistor. However, since a maximum voltage applied to a DRAM memory cell generally has a voltage level of VDD, a boosted voltage, which is higher than VDD plus Vt, should be applied to a gate of the NMOS transistor in order to read a voltage having a complete level of VDD from a cell or a bit line, or to write to a cell or a bit line.
Various efforts have been made to reduce a consumption current in semiconductor devices. For example, in DRAM devices, consumption current can be reduced in a self-refresh mode. In general, a current is consumed to store data in a memory cell during a refresh operation. Here, a self-refresh current means the current measured during a self-refresh time. To reduce the self-refresh current, it is required to increase a self-refresh period. However, to increase the self-refresh period, it is required to increase a data retention time, which is a time for respective memory cells to retain data. One of method to increase the data retention time includes increasing a back bias voltage VBB applied to a transistor of the respective memory cells. For example, when in a self-refresh mode, a method includes reducing an off-leakage current of a cell transistor and increasing the data retention time by elevating and providing a back bias voltage VBB pumped and output from a voltage pumping device.
As a result, a high voltage VPP is mainly a voltage for driving a word line of a DRAM device, and a back bias voltage VBB is a voltage that is applied to a forming area in a transistor of a memory cell in order to reduce the self-refresh current. For example, both the high voltage VPP and the back bias voltage VBB are generated in a pumping voltage generating circuit equipped with an oscillator and a voltage pump.
FIG. 1 is a schematic block diagram of a conventional pumping voltage generating circuit. In FIG. 1, a pumping voltage generating circuit includes a detecting unit 10, an oscillator 20, a first VPP pump 30, and a second VPP pump 40. The detecting unit 10 generates a detection signal ‘det’ based upon a comparison of levels between a reference voltage Vref and a pumping voltage VPP. When the detection signal ‘det’ is enabled, the oscillator 20 outputs an oscillating signal ‘osc’.
Both the first VPP pump 30 and the second VPP pump 40 receive the oscillating signal ‘osc’ as an input, and performs pumping operations. Here, the pumping voltage VPP is output from a common node (node A) to which the individual output terminals of the first and second VPP pumps 30 and 40 are connected.
However, the pumping voltage generating circuit is problematic in that a peak current increases instantaneously because the first and second VPP pumps 30 and 40 are driven at the same time.